1. Field of the Invention
The present invention relates to a differential signal output apparatus for interface signals outputted as differential signals on a transmission line in digital interfacing for serial communication and determination of the presence/absence of transmitted interface signals, and more particularly to a differential signal output apparatus and determination of the presence/absence of transmitted interface signals suitably usable for serial communicating having a high speed digital interface.
2. Description of the Related Art
According to the prior art, in high speed serial communication, typically represented by IEEE 1394 serial bus, differential signals are transmitted using a coaxial cable or a twisted pair cable as the transmission line. These differential signals have a differential amplitude of about 200 mV and a maximum data transfer rate of as fast as 400 megabits/sec according to the IEEE 1394-1995 standard, for instance.
Further in recent years, the P1394b standard is being formulated to realize high speed transmission over a long transmission distance as the next generation standard of IEEE 1394, as the voltage amplitude level of differential input signals and the like transmitted over a twisted pair cable or some other transmission line, high speed data transmission of about 800 mV in differential amplitude and 800 megabits/sec in maximum data transfer rate has come to be required, and circuit configurations with enhanced drive capacities for differential output signals to realize this high speed transmission are being devised.
According to the P1394b standard, there is required a signal detection circuit which detects the voltage amplitude level of differential input signals and the like transmitted over a twisted pair cable or some other transmission line; if it is not above a prescribed level, outputs the detect signal as a low level; if a voltage amplitude level not below the prescribed level is detected, determines it as a high level; and notifies the detection of input signals from the transmission line.
As a circuit configuration with an enhanced drive capacity for differential output signals, for instance, a differential signal output circuit 100 shown in FIG. 25 is conceived.
Referring to FIG. 25, the source terminals of PMOS transistors Q1 and Q2 are connected in common to a node N1, which is connected to a power supply voltage VDD via a first current source C1. The drain terminals of the PMOS transistors Q1 and Q2 are connected to the drain terminals of NMOS transistors Q3 and Q4 to constitute differential output terminals OUT and OUTX. The source terminals of the NMOS transistors Q3 and Q4 are connected in common to a node N2 to be connected to a ground voltage GND via a second current source C2. The gate terminal of the PMOS transistor Q1 and the gate terminal of the NMOS transistor Q3 are connected to constitute one differential input terminal IP, and the gate terminal of the PMOS transistor Q2 and the gate terminal of the NMOS transistor Q4 are connected to constitute the other differential input terminal IM.
In the PMOS transistor Q1 and the NMOS transistor Q3 configured into an inverter, and in the PMOS transistor Q2 and the NMOS transistor Q4 configured into another inverter, the PMOS transistors Q1 and Q2 on the one hand and the NMOS transistors Q3 and Q4 on the other respectively constitute first and second differential pairs. The current from the first current source C1 on the source current side is controlled which differential pair to go through to get to the second source C2 on the sink current side, i.e., to go through the first differential pair or the second differential pair. By mutually connecting these first and second differential pairs and using the connection points as the differential output terminals OUT and OUTX, it is made possible to directly drive the differential output terminals OUT and OUTX in the responses of differential outputs OUT and OUTX to differential inputs IP and IM by supplying source/sink currents to them, and fast responsiveness is thereby achieved.
However, in the differential signal output circuit 100 of FIG. 25, the source terminals of the PMOS transistors Q1 and Q2 and of the NMOS transistors Q3 and Q4 in the inverter configuration of the first differential pair Q1 and Q2 and the second differential pair Q3 and Q4 are respectively connected to the power supply voltage VDD via the first current source C1 and to the ground voltage GND via the second current source C2. Therefore, the voltage at the node N1 to which the source terminals of the PMOS transistors Q1 and Q2 are connected is lower than the power supply voltage VDD by the operating voltage of the first current source C1, and the voltage at the node N2 to which the source terminals of the NMOS transistors Q3 and Q4 are connected is higher than the ground voltage GND by the operating voltage of the second current source C2. Supposing here that first and second current sources C1 and C2 are current mirror circuits made up of MOS transistors and the threshold voltage of the MOS transistors is 0.7 V in absolute value, the operating currents of the first and second current sources C1 and C2 can be presumed to be around 1 V, though it depends on the transistor size and amperage. If the power supply voltage VDD is 3.3 V, the voltage applied between the source terminals of the first and second differential pairs Q1/Q2 and Q3/Q4 in the inverter configuration will be only about 3.3 V−1 V−1 V=1.3 V. As the threshold voltage of the MOS transistors is 0.7 V, the intermediate voltage at the operating points of the transistors Q1/Q3 and Q2/Q4 in the inverter configuration is 0.65 V (=1.3 V/2) from each source terminal. Whereas the operating points are the centers of input signal switching, all of the transistors Q1/Q3 and Q2/Q4 in the inverter configuration are turned off at these points. Thus, in a transitional state at the time the differential input signals are switched, there is a period in which all of the transistors Q1/Q3 and Q2/Q4 in the inverter configuration are turned off and current paths are cut off.
In the differential signal output circuit 100 of FIG. 25, the first and second current sources C1 and C2 keep on flowing constant currents all the time. Therefore, when the current paths are cut off, a current flows into the node N1 connected to the first current source C1, resulting in charging of parasitic capacitance components including the capacitance components and wiring capacitances of the source terminals of the transistors Q1 and Q2 connected to the node N1, whose voltage is thereby raised. Similarly a current flows out of the node N2 connected to the second current source C2, resulting in discharging of parasitic capacitance components including the capacitance components and wiring capacitances of the source terminals of the transistors Q3 and Q4 connected to the node N2, whose voltage is thereby lowered.
Upon termination of the switching period of the differential input signal, the transistors on the side having been non-conductive before the switching are conductive to connect the current paths again. Then, the charges/discharges which were effected when the current paths were cut off are discharged/charged via these current paths from or to the differential output terminals OUT and OUTX. Thus there is the problem of voltage overshooting/ undershooting at the differential output terminals OUT and OUTX immediately after the switching.
In the differential signal output circuit 100 of FIG. 25, a differential signal output circuit wherein either pair of the first and second differential pairs Q1/Q2 and Q3/Q4 in FIG. 25 is replaced with resistance elements or the like, or in a known differential signal output circuit provided with a passive load or an active load shown in FIG. 26 for use not only in high speed transmission but also in general applications, element characteristics may differ owing to fluctuations in manufacturing between the transistors Q1 and Q2, Q3 and Q4, Q5 and Q6 or Q7 and Q8. These difference in element characteristics may give rise to differences in response characteristics, resulting in a lag in operational timing at the time of differential input signal switching between the differential pairs Q1/Q2 through Q7/Q8 to turn off both the transistors Q1/Q2 through Q7/Q8 constituting the differential pairs. As the current paths from the current sources C1, C2, C3 and C4 are cut off in this case, too, the voltages of nodes N1, N2, N3 and N4 connected to the current sources C1 through C4 vary transitionally, inviting a problem that the varied voltages propagate to the differential output terminals at the timing of the next turning-on of the other transistors of the differential pairs Q1/Q2 through Q7/Q8 and give rise to overshooting or undershooting at the differential output terminals.
Further, if there is any difference in wiring delay in the differential input signals, a lag in the timing of switching will occur between the differential pairs Q1/Q2 through Q7/Q8. In this case, too, if the delay relationship is added in such a manner as will give rise to an off period for all of the differential pairs Q1/Q2 through Q7/Q8, there will again arise a problem that, as in the above-described case, voltage overshooting or undershooting occurs at the differential output terminals.
Under the P1394b standard, on the other hand, even high speed than the 400 Mbps of the conventional IEEE 1394 standard is contemplated, and high speed transmission standards from 800 Mbps (commonly known as the S800 standard) to 3.2 Gbps (commonly known as the S3200 standard) are formulated. In order to detect the voltage amplitude level of data signals at the transmission of the S3200 standard at the maximum by bit-by-bit sampling, the signal detection circuit is required by the Nyquist sampling theorem to operate at a high sampling frequency of no less than 6.4 GHz, double the frequency of 3.2 GHz. In order to realize a signal detection circuit required to operate at such a high speed, it is usually configured of a bipolar transistor whose cutoff frequency is higher than that of a MOS transistor.
FIG. 27 illustrates an example of signal detection circuit 1000 for detecting the voltage amplitude level of data signals bit by bit. Out of the differential input signals, an input signal IN+ on the positive logic side is entered into a peak hold circuit 1100. The peak voltage level of the input signal IN+ is supplied from the peak hold circuit 1100 and entered into a voltage level detector 1200. If the input signal IN+ is above a prescribed voltage level, the transmission of an effective differential input signal is assumed, and a signal-detect signal SD is set to a high level.
The peak hold circuit 1100 here consists of an the operational amplifier A1100, a diode D1100 and a capacitor C1100. The input signal IN+ is entered into the non-inverting input terminal of the operational amplifier A1100, and the output terminal of the operational amplifier A1100 is arranged for input to the anode terminal of the diode D1100. The cathode terminal of the diode D1100 is arranged for feedback to the inverting input terminal of the operational amplifier A1100 and connected to the capacitor C1100. Incidentally, a reset switch S1100 for discharging the capacitor C1100 is connected in parallel to the capacitor C1100 and controlled with a reset signal R.
Also, the voltage level detector 1200 is arranged for inputting from the output terminal of the peak hold circuit 1100 to the non-inverting input terminal, and a preset detection level voltage VREF is entered into the inverting input terminal.
Since the peak hold circuit 1100 constitutes a voltage follower circuit into which the diode D1100 is inserted in the forward direction, the entered input signal IN+ is supplied at the output terminal of the peak hold circuit 1100, which is the cathode terminal of the diode D1100. As the diode D1100 is inserted in the forward direction into a feedback path in the voltage follower configuration, the output voltage of the peak hold circuit 1100 can follow any rise in the input signal IN+, but, against a voltage drop of the input signal IN+ conversely, the inverse direction characteristic of the diode D1100 causes the output terminal of the peak hold circuit 1100 to maintain its output voltage. The capacitor C1100 connected to the output terminal of the peak hold circuit 1100 is provided to maintain the output voltage in this process. The reset switch S1100 is provided for resetting the peak voltage set in the peak hold circuit 1100 with the reset signal R.
The voltage level detector 1200 constitutes a comparator. It compares the output voltage entered into the non-inverting input terminal from the peak hold circuit 1100 with the output voltage entered into the inverting input terminal from the detection level voltage VREF. If the output voltage from the peak hold circuit 1100 is found lower than the detection level voltage VREF, a low level is outputted as the signal-detect signal SD if it is higher, inversion takes place to output a high level thereby to notify the detection of effective differential input signals.
As stated above, in order to sample the input signal IN+ bit by bit, a maximum sampling frequency of 6.4 GHz or more, double the 3.2 GHz (S3200 standard data transfer rate, is required. Therefore, the peak hold circuit 1100 and the voltage level detector 1200 have to be configured around high speed bipolar transistors.
However, although a bipolar transistor can help realize high speed operation, high speed operation of a circuit comprising a bipolar element requires a large bias current, making it difficult to realize less power consuming operation. The P1394b standard is expected to find increasing use in personal computers and portable equipment including mobile information terminals. Portable equipment is required to permit continuous battery-powered use for many hours and, because of the needed portability, high density packaging. Therefore, both with a view to extending the duration of continuous use and in view of the packaging limitation on the permissible heat generation from the chip, a signal detection circuit conforming to P1394b is required to operate without large current consumption, and the signal detection circuit of the above-described configuration involves the problem of inability to satisfy these requirements.
Furthermore, as is typically the case with high density packaging required by portable equipment, realization of diverse functions under the P1394b standard in a high density of integration requires a system LSI configuration constituted of CMOS transistors. It is preferable also to integrate into this system LSI a signal detection circuit for detecting differential input signals from the transmission path. However, as the cut-off frequency of a MOS transistor is lower than the cut-off frequency of a bipolar transistor, it is impossible to realize with a system LSI configured of CMOS transistors the detection of the voltage amplitude level of the differential input signals by bit-by-bit sampling, which is required under the P1394b standard. Therefore, it is inevitable to use a two chip configuration in which the signal detection circuit is constituted of a bipolar LSI and other functions are constituted of a system LSI consisting of CMOS transistors, resulting in a problem that a sufficiently high density of packaging may not be achieved.
It is further conceivable to develop a novel BiCMOS LSI permitting the packaging of the bipolar transistor part to realize the signal detection circuit and the CMOS transistor part to realize other functions into a single chip. However, development of a novel LSI permitting the realization of a high speed bipolar transistor on a single chip together with a minute CMOS transistor capable of integrating large scale circuits would take enormous time and money, which means the problem of difficulty to achieve the purpose at an appropriate timing and a reasonable cost.